Method for handling semiconductor layers in such a way as to thin same

ABSTRACT

This invention relates to a method for making a thin layer starting from a wafer comprising a front face with a given relief, and a back face, comprising steps consisting of: a) obtaining a support handle with a face acting as a bonding face; 
         b) preparing the front face of the wafer, this preparation including incomplete planarisation of the front face of the wafer, to obtain a bonding energy E 0  between a first value corresponding to the minimum bonding energy compatible with the later thinning step, and a second value corresponding to the maximum bonding energy compatible with the subsequent desolidarisation operation, the bonding energy E 0  being such that E 0 =α.E, where E is the bonding energy that would be obtained if the front face of the wafer was completely planarised, α is the ratio between the incompletely planarised area of the front face of the wafer and the area of the front face of the wafer if it were completely planarised; c) solidarising the front face of the wafer on the bonding face of the support handle, by direct bonding; d) thinning the wafer starting from its back face until the thin layer is obtained; e) transferring the thin layer onto a usage support, involving separation from the support handle.

TECHNICAL DOMAIN

Needs for electronic components that are very thin (between a few μm anda few tens of μm) are increasing. These ultra thin components have manyadvantages, principally their small size and considerable flexibility ofuse. For example, this type of electronic component can be integrated onplastic or paper supports. The first application is for smart cards andelectronic labels. Ultra-thin electronic components are alsoincreasingly in demand in domains such as encapsulation in order to makecircuits in ultra-flat boxes.

These ultra-thin components are also essential for making verticallyintegrated circuits or 3D circuits. Transfer of one ultra-thin circuitonto another circuit provides a means of increasing the integrationdensity in this manner. Applications of these 3D circuits apply to newintegrated power, radio frequency, optoelectronic systems and alsomicroprocessors.

It is also important to be able to obtain microsystem type components(in the broad Micro-Electro-Mechanical System (MEMS) sense orMicro-Optical-Electro-Mechanical Systems (MOEMS) sense) in very thinlayers to facilitate integration of these micro-systems with electroniccomponents and to obtain a completely integrated system.

In general, the so-called active layer of microelectronic components isonly between a few μm (or less) and a few tens of μm thick. Thereforethe interesting part of the component is only made on the surface ofwafers made from a semiconducting material. However, the thickness ofthe substrate plays an essential mechanical role when manufacturingintegrated circuits. The thickness of the substrate is what gives itsufficient mechanical strength, enables manipulation by standardautomated equipment and enables control over its planeness to achievethe necessary compatibility with high resolution photolithographyequipment processes. In other words, it is not feasible to produceintegrated circuits directly on films of semiconducting material a fewμm thick.

Therefore, there is a current need to reduce the thickness of the waferson which components are made.

Furthermore, this need for thinning is increasingly important becausethe thickness of new generations of wafers increases in proportion tothe diameter.

Therefore, a means has to be found for obtaining very thin electroniccomponents (typically less than 100 μm thick). One of the best means isa collective means in which thinning is done on the entire wafersupporting all components, rather than on a single component.

STATE OF PRIOR ART

At the moment it is extremely difficult to reduce the thickness ofwafers to very small values (less than 100 μm), causing yield problems.For such small thicknesses, the wafer becomes flexible and often breaksduring the thinning operation before stresses have been relaxed.

One known means of overcoming this problem is to glue the wafer onto anintermediate support called the support handle, so that the thinnedwafer can be held in place and manipulated without breaking. Thissupport handle enables the wafer containing the component to be madevery thin. After thinning, the thin layer obtained that is fixed to thesupport handle can be manipulated and transferred to another supportthat may be the final support.

Some methods that have been described include the techniques publishedin the article “Novel LSI/SOI Wafer Fabrication Using Device LayerTransfer Technique” by T. HAMAGUCHI et al., published in Proc. IEDM,1985, pages 688 to 691. This article mentions the use of a bond layer tosolidarise the substrate or the wafer to be thinned and the handlecomposed of an epoxy resin.

Other techniques based on the same principle were then developed usingdifferent means of bonding the substrate to be thinned onto the handle,for example such as resins or other glues. One example is the transferof treated layers onto a glass support by thermo setting UV glues.Further information about this subject is given in the article “An UltraLow-Power RF Bipolar Technology on Glass” by E. DEKKER et al., publishedin IEDM 1997, pages 921 to 923.

All presented techniques used a glue, in other words added material, tosolidarise the substrate to be thinned onto a support that may be thehandle or the final support. Although this additional layer producesvery strong bonding forces compatible with thinning, it modifies thethickness of the structure. It is also very difficult to control theglue thickness present and its homogeneity on the wafer. Thesecharacteristics cause a problem if uniform and precise thinning within afew micrometers is necessary. Moreover, the use of glue introducesanother problem if it is required to transfer the thin layer onto afinal support after thinning, and eliminate the intermediate supportthat acts as a handle. The bonding effect needs to be destroyed, forexample using a solvent. Two problems then arise. The first is that thesolvent is not always compatible with the final support, for example ifthe final support is a plastic smart card. The second problem is thatglue residues can remain that are sometimes difficult to remove.

There are other bonding methods that can be used to solidarise wafers toeach other. One method that is very advantageous is the direct waferbonding method. This technique is used in many domains to obtain somesubstrates, for example SOI substrates. For example, there is thewell-known example of the Smartcut® method described in the article byM. BRUEL published in Electron. Letters, 31 (1995), page 1201.

The principle of direct wafer bonding can be used to solidarise twowafers without adding any material, which is very useful for theapplication aimed at by the invention. To achieve this bond between twowafers, they must have good surface roughness properties, surfacechemistry properties (hydrophilic wafers for a hydrophilic glue orhydrophobic wafers for a hydrophobic glue), and planeness andcleanliness properties (no dust on the surface). For example, refer tothe document Semiconductor Wafer-Bonding: Science and Technology by I.GOESELE and Q. Y. TONG, in Electrochemical Society, published by JohnWiley and Sons, 1999.

However, the wafers on which electronic components are installed have arelief that makes it impossible to achieve the conditions required fordirect wafer bonding. To obtain the required roughness and reliefcriteria, it is often necessary to prepare the surfaces to be broughtinto contact, for example using a planarisation step bymechanical-chemical polishing. For example, these preparation techniquesare particularly suitable for bringing silicon oxide, silicon nitride orpolysilicon surfaces into contact (see C. GUI et al., J. Electrochem.Soc. 144, 1997, page 237). The surface relief is eliminated so as toobtain a maximum contact surface area so that bonding forces are as highas possible. The structures thus obtained are irreversibly solidarised.The documents mentioned above emphasize the need to perfectly planarisecontact surfaces over the entire wafer to obtain a good bond. The wafersare said to be perfectly planarised when the roughness AFM (rms) is lessthan or is of the order of 0.5 nm at all points. The roughness measuredby AFM (Atomic Force Microscope) corresponds to the roughness measuredby a tip in contact with the surface on a 100 μm² field.

This perfect planarisation is incompatible with wafers for which reliefis necessary, particularly to maintain openings at component contactpads.

The direct wafer bonding method is also used in domains other thanmicroelectronics, for example for manufacturing of micro-sensors orMEMS. In these other domains, some devices are made from solidarisationby direct bonding of wafers with a local recess or cavities. Informationon this subject is given in T. GESSNER et al., Proc. of second Internat.Symp. on microstructures and microfabricated systems (Elec. Soc. Inc.Pennington, N.J., USA, 1995), pages 297-308 (Chivago, Ill., USA, Oct.8-13, 1995). However, in these publications, the surfaces to besolidarised are prepared in such a way that bonding forces are veryhigh.

The technical literature has never reported the possibility ofseparating structures after bonding when a planarisation preparation hasbeen made, and when adhesion is followed by a consolidation heattreatment.

Furthermore, in their article on page 54 in their Materials Science andEngineering R report: “Wafer Direct Bonding: Tailoring Adhesion BetweenBrittle Materials”, A. PLOSSL et al. mention that if wafers aresolidarised by a hydrophilic gluing, subsequent annealing (for exampleat 100° C.) makes their separation difficult.

Other work has considered the possibility of controlling bonding forcesobtained by direct bonding of whole wafers with no relief. This controlover bonding forces provides a means of obtaining reversible bonding bycontrolling the roughness of the entire surface of the wafer. This isdescribed in document FR-A-2 796 491. If a wafer has any relief, thenthe entire surface of the wafer has to be made plane. This is done byeliminating the relief and attempting to obtain an rms value of thesurface roughness less than or of the order of 0.5 nm. The surfaceroughness is then modified homogeneously over the entire surface of thewafer.

Document FR-A-2 725 074 corresponding to American U.S. Pat. No.5,683,830 divulges the possibility of transferring thin layers from afirst substrate to a second substrate by controlling bonding forces.

In summary, prior art provides information about how to thin a wafer andglue it onto a support handle using different means. However, prior artdoes not describe any method that can be used to reversibly glue a waferincluding components and with a relief that has to be partly maintained,onto an intermediate part used as a handle, this bonding being such thatthe wafer can be thinned and that the thinned wafer can be manipulatedon its handle.

PRESENTATION OF THE INVENTION

The invention overcomes the problem described above.

Its purpose is a method for making a thin layer starting from a wafercomprising a front face divided into surface elements and with a givenrelief, and a back face, comprising steps consisting of:

-   -   a) obtaining a support handle with a face acting as a bonding        face;    -   b) preparing the front face of the wafer, this preparation        including incomplete planarisation of the front face of the        wafer, to obtain a bonding energy E₀ between the bonding face of        the support handle, between a first value corresponding to the        minimum bonding energy compatible with the later thinning step,        and a second value corresponding to the maximum bonding energy        compatible with the subsequent desolidarisation operation, the        bonding energy E₀ being such that E₀=α.E, where E is the bonding        energy that would be obtained if the front face of the wafer was        completely planarised, α is the ratio between the incompletely        planarised surface of the front face of the wafer and the        surface of the front face of the wafer if it were completely        planarised;    -   c) solidarising the front face of the wafer on the bonding face        of the support handle, by direct bonding;    -   d) thinning the wafer starting from its back face until the thin        layer is obtained;    -   e) transferring the surface elements from the thin layer onto a        usage support, involving separation from the support handle.

α is advantageously between 0.4 and 0.8.

According to a first application of the method, all surface elements aretransferred onto the usage support in step e).

According to a second application of the method, surface elements aretransferred individually in step e), step b) is carried out so as toobtain a bonding energy E₀ for each surface element, step e) beingpreceded by a step in which the thin layer is cut into surface elements.

According to a third application of the method, the surface elements aretransferred by groups of surface elements in step e), step b) is carriedout so as to obtain a bonding energy E₀ for each group of surfaceelements, step e) being preceded by a step in which the thin layer iscut into groups of surface elements.

The support handle may be cut at the same time as the thin layer is cut.

The cutting step may be made by combining a deep etching step of thethin layer and a sawing step.

In particular, the part of the wafer from which the thin layer will beobtained may include semiconducting material. The surface elements maybe composed of complete or incomplete electronic components.

In step b), the incomplete planarisation may be done by amechanical-chemical polishing method.

In step d), the wafer may be thinned by a mechanical, chemical ormechanical-chemical thinning method.

In step e), separation from the support handle may be achievedparticularly by mechanical and/or pneumatic means.

In step e), the transfer takes place before separation from the supporthandle.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood and other advantages andspecific features will become clear after reading the followingdescription, given as a non-limitative example, accompanied by theappended drawings, wherein:

FIG. 1 is a cross-sectional view of a support handle for using themethod according to the invention,

FIG. 2 is a cross-sectional view of a wafer that will be used to producea thin layer according to the method according to the invention;

FIGS. 3A to 3F illustrate different steps in the method according tothis invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

FIG. 1 is a cross-sectional view of a support handle 10, for examplecomposed of a silicon or glass wafer. Glass has the advantage of beingtransparent, so that objects deposited on the back face can be inspectedvisually. The support handle 10 has a face 11 prepared to act as abonding face.

FIG. 2 is a cross-sectional view of a wafer 20 made of a semiconductingmaterial, for example silicon. One of its main faces has been treated tomake electronic components. FIG. 2 is a partial view showing threecomplete or incomplete components 21. Due to the presence of thesecomponents, that the treated plane face has a large relief with severalareas of different heights and different roughnesses. When the wafercomprises complete components, part of this relief corresponds to thepresence of openings used to connect to electrical contacts.

In general, the chemical nature of the wafers to be bonded by molecularbonding, chemical cleaning before bonding and the bonding consolidationheat treatment are fixed such that a bonding energy E is obtained if thewafer on which the components are installed is fully planarised. Asurface is fully planarised if its roughness is less than about 0.5 nmin every 100 μm² element on this surface (AFM measurement).

In the method according to the invention, the wafer comprising thecomponents is prepared and then bonded onto the support handle so as toobtain molecular bonding with a controlled bonding energy E₀ such thatE₀=α.E where E₀>E₁ and E₀<E₂. E₁ is the minimum bonding energycompatible with thinning. E₂ is the maximum bonding energy below whichseparation of the bonded parts is reversible. The coefficient α isadvantageously between 0.4 and 0.8. This coefficient is the ratiobetween the planarised area and the total area of the wafer. Inpractice, the planarised area is equal to the sum of the elements of theplanarised area. A planarised surface element refers to any contiguouspart of the surface for which the roughness measured by AFM is less thanabout 0.5 nm on any 100 μm² element.

Solidarisation (or bonding) is done by direct wafer bonding,consequently there is no added material at the interface of the twosolidarised parts. The total thickness of the bonded parts is notchanged and thinning can be done very precisely. This precision thendepends on the equipment used. If mechanical thinning is done, aprecision of + or less 1 μm can be obtained.

FIGS. 3A to 3D illustrate different steps in the method according to theinvention.

FIG. 3A shows the wafer 20 after the planarisation operation done untillevel 22 is reached. Planarisation is preferably done by mechanicalchemical polishing (CMP) so as to clip relief vertices sufficiently toobtain molecular bonding but without completely planarising the wafer,unlike normal practice. There is still some relief on the wafer onseveral levels. Only two levels are shown in FIG. 3A, but there may bemore than two levels.

The bonding energy E₁ corresponds to the minimum bonding energy thatenables thinning. Obviously, this minimum energy depends on the thinningmethod that may be mechanical, chemical, mechanical-chemical or other.For example, E₁ is equal to 500 mJ/m² for thinning by grinding andmechanical-chemical polishing.

FIG. 3B shows the structure obtained when the wafer 20 is solidarised bymolecular bonding on the components side with the support handle 10. Thebonding energy E depends on the temperature at which the structure wasannealed (if annealing is done), the nature of the materials that areput into contact (Si₃N₄, SiO₂, Si, etc.) and chemical cleaningtreatments that are done before bringing into contact. Therefore, heatand chemical treatments are always chosen so as to not degrade thestructure and particularly the components present. For example, for ahydrophilic bonding of two totally planarised SiO₂—SiO₂ surfaces, anenergy of 1 J/m² is obtained after annealing at 300° C. for two hours.The bonding energy E₂ is the maximum bonding energy below whichsolidarisation is reversible. Obviously, it depends on the method usedto separate the two wafers at the bonding interface after thinning. Forexample, if a blade is used to separate the two parts of the structure,E₂ is equal to about 800 mJ/m² (bonding energies are measured using theblade method).

The wafer 20 bonded onto the support handle 10 is thinned through itsback face to give a thin layer 23. This is shown in FIG. 3C. Thisthinning may be done mechanically (polishing or grinding). It may bechemical by etching using a solution that attacks the material to bethinned. It may also be mechanical-chemical; by chemical-mechanicalpolishing. A stop layer may also be present in the initial substrate(for example a buried oxide layer in the case of an SOI substrate). Inthis case, thinning is done as far as this stop layer.

After thinning, the thin layer solidarised with the support handle canbe manipulated. The components of the thin layer may then be transferredcollectively onto another support with the same diameter. They may alsobe transferred individually. If an individual transfer is requested, thecomponents are cut on their support handle. FIG. 3C shows the cut axes24 of the components 21.

FIG. 3D shows the components and their cut supports. These cutcomponents can be handled with conventional tools since the thinnedcomponents are on their handling support. FIG. 3D shows a component 21and the part of the support handle 10 corresponding to it, duringhandling.

Once the component(s) is (are) transferred onto its (their) finalsupport or onto another intermediate support, it must be possible toseparate the component(s) from its (their) part of the support handle.FIG. 3E shows a component 21 transferred onto its final support 25, thecomponent 21 still being fixed to its part of the support handle 10.FIG. 3F shows the component 21 fixed on its final support 25 andseparated from its part of the support handle 10. Separation may be doneby any mechanical or pneumatic means used by itself or in combination.For example there is separation by insertion of a tool (Teflon® blade,metallic), by injection of a gas flow, applying a tension and/or shearforce.

One variant of this method consists of only cutting the thin layercontaining the elements to be transferred, or only this layer and partof the handle. The element to be transferred is then picked up at thesame time as the separation between the element and the support handle.A manipulator (for example a vacuum micro-pipette) is used to transferthe element.

In another variant, the component may be separated from the supporthandle during the transfer. This is the case when a punch is usedthrough a hole in a support handle.

The invention is applicable to thinning of any type of semiconductor,for example silicon, germanium, III-V semiconductors (AsGa, InP, GaN,etc.) It is also applicable to the case in which the wafer is made froman arbitrary material but which can be thinned.

We will now describe the case of a wafer comprising integrated circuitson the surface in which the contact pins are open and for which theelectrical characteristics have been tested using a standard tester.This wafer has strong relief on the surface. If thinning has to be wellcontrolled, the wafer is measured precisely before thinning to determinethe thicknesses at all points of this wafer (for example by ADE).

The wafer is incompletely planarised so as to clip the peaks of therelief and to obtain plateaux with a surface area of about 2 mm² andwith a roughness of less than 0.5 nm. For example, this surface may besilicon oxide or a silicon nitride. The planarised surface occupies 60%of the total area. Planarisation is done by CMP and after chemicalcleaning, the wafer is brought into contact with its support handle thatmay be a silicon wafer oxidised on the surface or a glass wafer possiblywith a deposition of silicon oxide on the surface. This wafer is thenannealed at 250° C. for two hours to obtain a bonding energy of theorder of 600 mJ/m². It is also possible to heat to a lower temperatureand for a longer period, or vice versa to obtain a bonding energy of thesame order of magnitude.

The back face of the wafer containing the integrated circuits is thinnedto a thickness of 10 μm, for example by grinding followed bymechanical-chemical polishing. The circuits are then cut out with theirsupport handle using a standard saw. One variant consists of deepetching the thin layer carrying components according to a pattern thatfacilitates sawing, for example etching over the entire length of thethin layer over a length longer than the saw line. The assembly ismanipulated with standard “pick and place” type tools. For example, acircuit may then be transferred onto a smart card by gluing the backface of the circuit onto the final support with glue. Tension is thenapplied so as to separate the front face of the circuit from the supporthandle.

According to another variant embodiment, the back face of the circuit isbonded by direct wafer bonding onto a wafer containing other circuits inorder to produce 3D circuits. The back face of the circuit may besolidarised, for example with a bonding energy equal to 1.5 J/m². Thisenergy can be obtained using plasma cleaning. The intermediate supportmay be eliminated by inserting a blade at the bonding interface. A smallrecess may be provided at the interface to make it easier to insert theblade.

1. Method for making a thin layer starting from a wafer comprising afront face divided into surface elements and with a given relief, and aback face, comprising steps consisting of: a) obtaining a support handlewith a face acting as a bonding face; b) preparing the front face of thewafer, this preparation including incomplete planarisation of the frontface of the wafer, to obtain a bonding energy E₀ with the bonding faceof the support handle, between a first value corresponding to theminimum bonding energy compatible with the later thinning step, and asecond value corresponding to the maximum bonding energy compatible withthe subsequent desolidarisation operation, the bonding energy E₀ beingsuch that E₀=α.E, where E is the bonding energy that would be obtainedif the front face of the wafer was completely planarised, α is the ratiobetween the incompletely planarised surface of the front face of thewafer and the surface of the front face of the wafer if it werecompletely planarised; c) solidarising the front face of the wafer onthe bonding face of the support handle, by direct bonding; d) thinningthe wafer starting from its back face until the thin layer is obtained;e) transferring the surface elements from the thin layer onto a usagesupport, involving separation from the support handle.
 2. Methodaccording to claim 1, wherein α is between 0.4 and 0.8.
 3. Methodaccording to claim 1, wherein all surface elements are transferred ontothe usage support in step e).
 4. Method according to claim 1, whereinsurface elements are transferred individually in step e), step b) iscarried out so as to obtain a bonding energy E₀ for each surfaceelement, step e) being preceded by a step in which the thin layer is cutinto surface elements.
 5. Method according to claim 1, wherein surfaceelements are transferred by groups of surface elements in step e), stepb) is carried out so as to obtain a bonding energy E₀ for each group ofsurface elements, step e) being preceded by a step in which the thinlayer is cut into groups of surface elements.
 6. Method according toclaim 4, wherein the support handle is cut at the same time as the thinlayer is cut.
 7. Method according to claim 4, wherein the cutting stepis made by combining a deep etching step of the thin layer and a sawingstep.
 8. Method according to claim 1, wherein the part of the wafer fromwhich the thin layer will be obtained includes semiconducting material.9. Method according to claim 8, wherein the surface elements arecomposed of complete or incomplete electronic components.
 10. Methodaccording to claim 1, wherein in step b), the incomplete planarisationis done by a mechanical-chemical polishing method.
 11. Method accordingto claim 1, wherein in step d), the wafer is thinned by a mechanical,chemical or mechanical-chemical thinning method.
 12. Method according toclaim 1, wherein in step e), separation from the support handle isachieved particularly by mechanical and/or pneumatic means.
 13. Methodaccording to claim 1, wherein in step e), the transfer takes placebefore separation from the support handle.
 14. Method according to claim5, wherein the cutting step is made by combining a deep etching step ofthe thin layer and a sawing step.